====== VIM3 and VIM3L v14 ======

[[:VIM3]] and [[:VIM3L]] start from revision ''v14'' have another DRAM configuration.


====== Un-bootable images ======

Some images and OS distros still can use old boot-loaders blobs which not compatible with new hardware revisions  v14.

Solution: 
  * rewrite/update boot-loader
  * WIP:


====== Broken boot-loader stuck in loop  ======

This issue happens 

  * After writing old U-Boot into internal eMMC storage for new board rev ''v14''
  * or latest U-Boot images for SPI-flash

easiest way to fix it just re-flash the device with Amlogic burn tool by suitable eMMC U-Boot image to restore it

https://github.com/khadas/khadas-uboot/releases/download/0.16.4/VIM3.uboot-mainline.emmc.aml.img

```sh restore-vim3-device-uboot.sh
curl -OjkL https://github.com/khadas/khadas-uboot/releases/download/0.16.4/VIM3.uboot-mainline.emmc.aml.img
## reset device into usb-burn-mode
aml-burn-tool -b VIM3 -i VIM3.uboot-mainline.emmc.aml.img
## reboot 
```
===== Write U-Boot to SPI flash =====

<WRAP important >
  * revision board v12 works
  * can works for some revision board v14 - some boards have different DDR
</WRAP>

==== Latest suitable SPI-uboot ====


https://github.com/khadas/khadas-uboot/releases/download/0.16.4/VIM3.u-boot.spi.bin

```sh oowow-shell-write-uboot-to-spi-flash.sh
curl -OjkL https://github.com/khadas/khadas-uboot/releases/download/0.16.4/VIM3.u-boot.spi.bin
spi_update < VIM3.u-boot.spi.bin
mmc_boot_erase
kbi bootmode spi
kbi poweroff
```

```log vim3-v12-spi-uboot-0.16.4.log
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 58159

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00012ab5
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 8
Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SPI, src: 0x00060000, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SPI, src: 0x00038000, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SPI, src: 0x0003c000, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SPI, src: 0x00048000, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==87 ps 9
TxDqDly_Margin_A1==97 ps 10
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==26
VrefDac_Margin_A0==27
DeviceVref_Margin_A0==26
VrefDac_Margin_A1==28
DeviceVref_Margin_A1==26


channel==1
RxClkDly_Margin_A0==97 ps 10
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==106 ps 11
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==25
TrainedVREFDQ_A1==23
VrefDac_Margin_A0==26
DeviceVref_Margin_A0==24
VrefDac_Margin_A1==26
DeviceVref_Margin_A1==23

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 

soc_vref_reg_value 0x 00000027 00000028 00000028 00000027 00000027 00000026 00000026 00000028 00000028 00000026 00000027 00000027 00000026 00000027 00000026 00000025 00000027 00000027 00000025 00000029 00000025 00000026 00000025 00000027 00000026 00000025 00000024 00000027 00000025 00000026 00000026 00000026 dram_vref_reg_value 0x 00000013
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

100bdlr_step_size ps== 409
result report
boot times 0Enable ddr reg access
Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SPI, src: 0x00078000, des: 0x01768000, size: 0x000ac000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 1c 07 00 00 14 37 34 43 59 53 50 
[0.018961 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):4fc40b1
NOTICE:  BL31: Built : 15:58:17, May 22 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2021.07 (Nov 12 2021 - 11:31:01 +0800) khadas-vim3

Model: Khadas VIM3
SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
DRAM:  3.8 GiB
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from MMC... ignored booted from other source!
Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
```

```log vim3-v14-spi-uboot-0.16.4.log
G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 58272

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 10
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 00012b7d
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 10
Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SPI, src: 0x00060000, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SPI, src: 0x00038000, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SPI, src: 0x0003c000, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 4, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from SPI, src: 0x0003c000, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SPI, src: 0x00048000, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==87 ps 9
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==29
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==31
DeviceVref_Margin_A0==29
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0


channel==1
RxClkDly_Margin_A0==106 ps 11
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==29
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==30
DeviceVref_Margin_A0==29
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004 

soc_vref_reg_value 0x 00000025 00000027 00000027 00000027 00000027 00000028 0000002a 00000026 00000027 00000026 00000025 00000027 00000026 00000027 00000027 00000027 00000025 00000027 00000027 00000026 00000026 00000028 00000026 00000026 00000027 00000026 00000025 00000026 00000027 00000025 00000024 00000027 dram_vref_reg_value 0x 00000014
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002cDDR size: 2048MB
cs0 DataBus test pass
cs0 AddrBus test pass

100bdlr_step_size ps== 457
result report
boot times 0Enable ddr reg access
Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SPI, src: 0x00078000, des: 0x01768000, size: 0x000ac000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 19 10 00 00 16 30 34 33 42 42 50 
[0.018959 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):4fc40b1
NOTICE:  BL31: Built : 15:58:17, May 22 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2021.07 (Nov 12 2021 - 11:31:01 +0800) khadas-vim3

Model: Khadas VIM3
SoC:   Amlogic Meson G12B (A311D) Revision 29:b (10:2)
DRAM:  2 GiB
MMC:   sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from MMC... ignored booted from other source!
Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
```
====== Compatible images for any hw revisions ======

  * https://github.com/khadas/khadas-uboot/releases
  * https://dl.khadas.com/products/vim3/firmware/uboot/mainline/
  * https://dl.khadas.com/products/vim3l/firmware/uboot/mainline/
  * https://dl.khadas.com/products/oowow/system/vim3-oowow-latest-sd.img.gz
  * https://dl.khadas.com/products/oowow/system/vim3l-oowow-latest-sd.img.gz
  * https://dl.khadas.com/.images/vim3/
  * https://dl.khadas.com/.images/vim3l/